First Results of ITC'99 Benchmark Circuits

54 0740-7475/00/$10.00 © 2000 IEEE IEEE Design & Test of Computers BENCHMARKS ARE IMPORTANT vehicles that let industry and academia develop new tools, compare and contrast different methodologies, and research new algorithms and techniques. In design-for-testability (DFT) work, the standard sets have been the International Symposium on Circuits and Systems (ISCAS) ’85 and ’89 circuits.1,2 These circuits have been in longtime use over many years and much theoretical work has been done using them as a basis. However, evolution of both design styles and tools calls for new, larger, and more complex circuits that more closely represent current technology. Table 1 lists the set of circuits in the ITC’99 benchmark portfolio (http://www.cerc.utexas. edu/itc99-benchmarks/bench.html). It includes several designs from industry, the Torch design from Stanford University, the Carnegie Mellon University digital signal processor (CMUDSP) design, and a group of circuits from Polytechnic University of Torino. This article examines the I991, I992, and I99C1 circuits in some detail because they are already in structural Verilog format and gives a brief overview of 1994 and 1995 circuits. One requirement for the ITC’99 benchmarks was that they be written in either of two hardware description languages—Verilog or VHSIC hardware description language (VHDL)—since most electronic design automation (EDA) tools, as well as some freeware simulators, support them. All the circuits are available in register transfer level (RTL) Verilog except the Torino benchmarks, which are in VHDL. Although it would be desirable to provide both Verilog and VHDL equivalents for all benchmarks, as Table 1 shows, these circuits are available in either, but not both. To do so would entail the additional task of verifying that the Verilog and VHDL netlists are logically equivalent, a worthwhile undertaking that will make the benchmarks more useful to a wider audience.